This invention relates to a semiconductor memory, to and from which data can be continuously inputted and outputted. A prior art semiconductor memory of this type will now be described in connection with 4-bit parallel data processing with reference to FIG. 1 and 2.
FIG. 1 is a block diagram showing a prior art semiconductor memory. Referring to FIG. 1, reference numeral 1 designates a serial data input circuit, 2 a writing circuit, 3 bit lines, 4 a column decoder, 5 a reading circuit, 6 a serial data output circuit, 7 a sense amplifier, and 8 a memory cell array. In memory cell array 8, memory cells 30 are connected to word lines 13 and bit lines 3. Reference numeral 9 designates an address generator, 10 a column address buffer, 11 a row address buffer, 12 a row decoder, 17 a clock signal, and 32 data transfer lines. Serial data input circuit 1 and writing circuit 2 connected thereto function to convert continuously supplied input data into 4-bit parallel data and supply these 4-bit parallel data through bit lines 3 to column decoder 4. Reading circuit 5 and serial data output circuit 6 connected thereto function to sequentially and continuously provide 4-bit data read out through column decoder 4. Serial data input and output circuits 1 and 6 are constituted by shift registers or the like. Column decoder 4 consists of a plurality of 4-bit column groups C1 to Cn.
Bit lines 3 extend through column decoder 4 and sense amplifier 7 into memory cell array 8 and are connected to respective pluralities of memory cells 30. Address generator 9 designates read or write addresses of memory cell array 8 to provide instructions to column and row decoders 4 and 12 through respective column and row address buffers 10 and 11, which can temporarily store addresses for every 4 bits. The temporarily stored addresses are instructed from column and row decoders 4 and 12 as respective intersections of bit and word lines 3 and 13.
The operation of the prior art semiconductor memory having the above construction will now be described with reference to FIG. 1 and operational timing chart of FIG. 2.
Referring to FIG. 1, clock 17 for generating a sync signal is connected to address generator 9. Row address signal 50 from address generator 9 is supplied through row address buffer 11 to row decoder 12 to activate a word line corresponding to the row address represented by the signal, for instance word line 13-1. Meanwhile, data supplied to serial data input circuit 1 as 4-bit parallel data is supplied to writing circuit 2. At the same time, according to column address signal 52 from address generator 9 a corresponding column group, for instance column group C1, is selected through column address buffer 10 to activate bit line 3-1 connected to selected column group C1.
When bit line 3-1 connected to column group C1 of column decoder 4 activated, data B1 is read out from memory cells 30-1 to 30-4 connected to activated word line 13-1 and activated bit line 3-1. More specifically, data B1 is read out from memory cell array 8 through bit line 31, sense amplifier 7, column group C1 in sense amplifier 7 and reading circuit 5. Then, write address 53 is supplied to column group C1, and data A1 is written by writing circuit 2 through sense amplifier 7 and bit line 3-1 in memory cells 30-1 to 30-4 connected to activated word line 13-1 and activated bit lines 3-1 of memory cell array 8.
Then, with word line 13-1 held in the activated state, column group C2 is selected as column address 52, and data B2 in memory cells 30-1 to 30-4 is read out. Then, column group C2 is selected as write address 53, and data A2 is written in memory cells 30-5 to 30-8. In the above way, data is read out from and written in memory cells connected to word line 13-1. After the reading and writing of data are done sequentially with respect to memory cells connected to one word line 13-1, a different word line, for instance word line 13-2, is activated, and like sequence of operations is performed.
As shown in FIG. 2, a delay time until input data is written as data A1 in memory cell array 8 and a delay time until data B1 read out from memory cell array 8 is provided as serial data are produced. These delay times are attributable, in addition to ordinary writing delays, greatly to delay produced at least for 4 bits when continuously supplied input data is converted in serial data input circuit 1 into 4-bit parallel signal and when 4-bit parallel signal is converted in serial data output circuit 6 into continuous data. Therefore, there result absence of data when 4-bit data 1 is supplied and input of data 3 when data B1 is provided.
Therefore, the prior art semiconductor memory has a problem in that the address of serial data output simultaneously with serially input data is not identical. This problem will be discussed in detail with reference to FIG. 3. FIG. 3 shows a prior art video signal processing system. In FIG. 3, reference numeral 101 designates a semiconductor memory storing signal, 102 a signal input terminal, 103 a signal output terminal, 104 and 105 transfer circuits for transferring signals, 106 an operational circuit for processing signals from transfer circuits 104 and 105. A video signal for one frame is supplied to signal input terminal 102 and transferred through transfer circuit 104 to operational circuit 106. Meanwhile, a video signal stored in semiconductor memory 101 is transferred through transfer circuit 105 to operational circuit 106. Operational circuit 106 processes the two video signals to produce an output which is provided from output terminal 103. This system is utilized when detecting a motion in video or when compensating for deviation or noise of image display. The signals from transfer circuit 104 and 105, which are processed in operational circuit 106, form one frame and, therefore, should be identical with one another in address. Therefore, when the video signal processing system as shown in FIG. 3 uses the prior art semiconductor memory, there arises a lack of address identity of combined video signals, and it is necessary to effect an address correction provide address identity, which is an inconvenient step. More specifically, lack of address identity of simultaneously input and output data dictates provision of address correction circuit 107 and the like when incorporating a prior art semiconductor memory in a system using different elements, for instance the video signal processing system shown in FIG. 3, to permit correction such as to permit simultaneous input and output of identical address data. This means that delay circuits and other elements have to be assembled separately for use, thus increasing the number of elements in use.